Dr. Surbhi Chhabra
Institute of Engineering and Technology
Education
- Ph.D. (Electronics and Communication Engineering) from The LNM Institute of Information Technology, Jaipur
- M.Tech. (Electronics and Communication Engineering) from The LNM Institute of Information Technology, Jaipur
- B.Tech. (Electronics and Communication Engineering) from Marudhar Engineering College, Bikaner (Rajasthan Technical University, Kota)
Experience
- Dr. Surbhi Chhabra is Assistant Professor of Electronics and Communication Engineering at the Institute of Engineering and Technology, JKLU. She holds a PhD with a major in Hardware Security from The LNM Institute of Information Technology, Jaipur.
- Prior to JKLU, Dr. Surbhi worked as Hardware Security Consultant at Data Security Council of India, Noida. She has published numerous peer-reviewed journals, conferences papers and book chapters of high repute. She is also serving as reviewers of IEEE Consumer Electronics Magazine, IEEE Access, IET Information Security, IET Electronics Letter, Springer International Journal of Information Security, and conferences like IEEE NCC etc.
Teaching Interests
- Programming-1
- Digital Circuits and Systems
- Computer Organisation and Architecture
- Digital System Design using FPGAs
- Hardware Security
Research Interests
- Hardware Security: Hardware Obfuscation, Physical Unclonable Functions
- Digital System Design using FPGAs
Honours, Awards, and Affiliations
- Qualified GATE-2014
- Recipient of IEEE VLSID (2022-23) Fellowship.
- Served as a Reviewer for peer reviewed journals vi. IEEE Consumer Electronics Magazine, IET Electronics Letters, IET Information Security, IEEE Access, Springer IJIS, and conferences like IEEE NCC.
- Served as a Session Chair in IEEE ICACCI Conference 2017.
- Received B.Tech. Honours in ECE & won the Best Student Award.
Selected Publications
- S. Chhabra and K. Lata, “Obfuscated AES cryptosystem for secure medical imaging systems in IoMT edge devices,” Health and Technology, vol. 12, no. 5, pp. 971–986, Aug. 2022, doi: 10.1007/s12553-022-00686-3.
- S. Chhabra and K. Lata, “Hardware obfuscation of AES IP core using combinational hardware Trojan circuit for secure data transmission in IoT applications,” Concurrency and Computation: Practice and Experience, vol. 34, no. 21, May 2022, doi: 10.1002/cpe.7058.
- S. Chhabra and K. Lata, “Hardware Obfuscation of AES IP Core Using PUFs and PRNG: A Secure Cryptographic Key Generation Solution for Internet-of-Things Applications,” SN Computer Science, vol. 3, no. 4, May 2022, doi: 10.1007/s42979- 022-01194-x.
- S. Chhabra and K. Lata, “Towards the enhancement of AES IP security using hardware obfuscation technique: A practical approach for secure data transmission in IoT,” SECURITY AND PRIVACY, vol. 5, no. 4, Apr. 2022, doi: 10.1002/spy2.233.
- K. Lata, S. Chhabra, and S. Saini, “Hardware–Software Co-Design Framework for Data Encryption in Image Processing Systems for the Internet of Things Environment,” IEEE Consumer Electronics Magazine, vol. 11, no. 4, pp. 92–97, Jul. 2022, doi: 10.1109/mce.2021.3115999.
Book Chapters
- S. Chhabra, S. Saini and K. Lata, “Hardware–software co-simulation of vehicle license plate detection on the ZedBoard SoC platform,”Advances in Image and Data Processing using VLSI Design, vol. 01, series 2053-2563, IOP Publishing, pp. 15-1 to 15-19, Dec 2021, doi: 10.1088/978-0-7503-3919-3ch15.
- S. Chhabra and K. Lata, “Key-Based Obfuscation Using Strong Physical Unclonable Function: A Secure Implementation”. In: Abraham, A., Shandilya, S., Garcia-Hernandez, L., Varela, M. (eds) Hybrid Intelligent Systems. HIS 2019. Advances in Intelligent Systems and Computing, vol 1179, Springer, Cham. doi: 10.1007/978-3-030-49336-3_39.
Conferences
- S. Chhabra and K. Lata, “Key-based Obfuscation using HT-like Trigger Circuit for 128-bit AES Hardware IP Core,” 34th IEEE International System-on-Chip Conference (SOCC), 2021, pp. 164-169, doi: 10.1109/SOCC52499.2021.9739619.
- S. Chhabra, V. Dhanwani, V. K. Dhaka and K. Lata, “Design and Analysis of Secure One-way Functions for the Protection of Symmetric Key Cryptosystems,” 24th IEEE International Symposium on VLSI Design and Test (VDAT), 2020, pp. 1-6, doi: 10.1109/VDAT50263.2020.9190432.
- S. Chhabra and K. Lata, “Hardware Software Co-Simulation of Obfuscated 128-Bit AES Algorithm for Image Processing Applications,” 4th IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2018, pp. 191-194, doi: 10.1109/iSES.2018.00049.
- S. Chhabra and K. Lata, “Design and Analysis of Logic Encryption Based 128-Bit AES Algorithm: A Case Study,” 15th IEEE India Council International Conference (INDICON), 2018, pp. 1-6, doi: 10.1109/INDICON45594.2018.8987098.
- S. Chhabra and K. Lata, “Enhancing Data Security using Obfuscated 128-bit AES Algorithm – An Active Hardware Obfuscation Approach at RTL Level,” 7th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2018, pp. 401-406, doi: 10.1109/ICACCI.2018.8554562.
- A. Bhardwaj, S. Chhabra and K. Lata, “FPGA Implementation of Traffic Light Controller and its Analysis in the Presence of Hardware Trojan,” 7th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2018, pp. 375-380, doi: 10.1109/ICACCI.2018.8554439.
- S. Chhabra and K. Lata, “Analysis of aes cryptosystem in the existence of hardware trojan,” 6th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2017, pp. 2335-2341, doi: 10.1109/ICACCI.2017.8126195.
- S. Chhabra and K. Lata, “Obfuscation based Secure 128-bit AES Algorithm Design at the RTL Level,” 5th Global Conference on Cyber Space (GCCS), 2017 Organized by Ministry of Electronics and Information Technology (MEITY), Government of India. (Poster Presented).
- S. Chhabra, H. Jain, and S. Saini, “FPGA based hardware implementation of automatic vehicle license plate detection system,” 5th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2016, pp. 1181-1187, doi: 10.1109/ICACCI.2016.7732205.
