Dr. Gaurav Mani Khanal is Assistant Professor in the Department of Electronics Engineering at the Institute of Engineering and Technology, JKLU. He has more than 5 years of teaching and research experience in India and Abroad. He completed PhD in Electronics Engineering with focus on Modelling, Fabrication and Application (system development) of novel nanoelectronics device (Memristor) for low power brain inspired electronics system design, from the University of Rome Tor Vergata, Rome, Italy. Dr. Gaurav have hands- on experience on electronics device modeling and circuit design using SPICE and digital system design and synthesis using VERILOG HDL.

Prior to joining the JKLU, he worked as Assistant Professor and Co-coradinator semiconductor research centre at Punjab Engineering College (Deemed to be University), Chandigarh, and also worked as post doctoral research fellow with Professor Gian Carlo Caradrillli’s The Hardware Architecture for Digital Signal Processing Lab located in the Department of Electronic Engineering of University of Rome Tor Vergata.

Dr. Gaurav has expertise in Memristor/Resistive switching device design, modeling, fabrication and characterization. He is an expert user of Spice tools for modeling of CMOS as well as beyond CMOS devices and circuits. He has published two books on VLSI design and has more than more than 12 research articles in the area of Memristor, VLSI design and novel nano-electronics and MEMS devices. He along with Semiconductor research centre team headed by Prof Arun Kumar Singh had organized two  7 days hands on workshops fully sponsored by SERB and DST GOI on Semiconductor devices design modeling, fabrication and characterization.

Recently his Project as (CO-PI) Titled “Memristor- FPGA hybrid hardware system for brain inspired analog computing” has received Funding from Ministry of Electronics & Information Technology (MeitY) under Chips to Start-up (C2S) programme. The project is in collaboration with Dr Arun Kumar Singh (PI) Professor and Co-coordinator of Semiconductor Research Centre, Department of ECE, Punjab Engineering College, Chandigarh and Dr Sanjeev Kumar(CO-PI) Professor & Head (Physics Department), Punjab Engineering College, Chandigarh. Technical collaborators for the projects are Sankalp Semiconductor an HCL Tech Company and Professor Gian Carlo Caradrilli’s Hardware Architectures for Digital Signal Processing Lab, Department of Electronics Engineering, University of Rome “Tor Vergata”, Rome, IT.
Duration: 5 years (Starting 2023) Total Amount: 81 Lakh INR