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Dr. Surbhi Chhabra

Assistant Professor

Computer Science Engineering

Institute of Engineering & Technology

Biography

Dr. Surbhi Chhabra holds a PhD from The LNM Institute of Information Technology, Jaipur, in Electronics and Communication Engineering with focus on Security of 128-Bit AES IP Core by using RTL Hardware Obfuscation Techniques. She received her Bachelor of Technology in 2014, and Master of Technology in 2016. Currently, she is working as Assistant Professor in the Institute of Engineering and Technology (Department of Computer Science and Engineering) at JK Lakshmipat University, Jaipur. Prior to joining JKLU, she was a hardware security consultant at Data Security Council of India. She has published and reviewed many papers in refereed journals, magazines, book chapters, and recognized conferences. Her research interests include Digital System Design using FPGAs, Hardware Security, Hardware Obfuscation for Cryptosystems, and Physical Unclonable Functions.

Education

  • The LNM Institute of Information Technology, Jaipur, 2023

    Ph.D

    Focus: Enhanced Security and Protection of 128-Bit AES IP Core by using RTL Hardware Obfuscation Techniques with Minimal Design Overheads

  • The LNM Institute of Information Technology, Jaipur, 2016

    MTech

    Major: Electronics and Communication Engineering

  • Marudhar Engineering College, Bikaner, 2014

    BTech

    Major: Electronics and Communication Engineering

  • Digital System Design using FPGAs
  • Hardware Security
  • Hardware Obfuscation for Cryptosystems
  • Physical Unclonable Functions Measurement

  • S. Chhabra and K. Lata, “Obfuscated AES cryptosystem for secure medical imaging systems in IoMT edge devices,” Springer Health and Technology, vol. 12, no. 5, pp. 971–986, Aug. 2022, doi: 10.1007/s12553-022-00686-3.
  • S. Chhabra and K. Lata, “Hardware obfuscation of AES IP core using combinational hardware Trojan circuit for secure data transmission in IoT applications,” Wiley Concurrency and Computation: Practice and Experience, vol. 34, no. 21, May 2022, doi: 10.1002/cpe.7058.
  • S. Chhabra and K. Lata, “Hardware Obfuscation of AES IP Core Using PUFs and PRNG: A Secure Cryptographic Key Generation Solution for Internet-of-Things Applications,” Springer SN Computer Science, vol. 3, no. 4, May 2022, doi: 10.1007/s42979-022-01194-x.
  • S. Chhabra and K. Lata, “Towards the enhancement of AES IP security using hardware obfuscation technique: A practical approach for secure data transmission in IoT,” Wiley Security and Privacy, vol. 5, no. 4, Apr. 2022, doi: 10.1002/spy2.233.
  • K. Lata, S. Chhabra, and S. Saini, “Hardware–Software Co-Design Framework for Data Encryption in Image Processing Systems for the Internet of Things Environment,” IEEE Consumer Electronics Magazine, vol. 11, no. 4, pp. 92–97, Jul. 2022, doi: 10.1109/mce.2021.3115999.

  • S. Chhabra, S. Saini and K. Lata, “Hardware–software co-simulation of vehicle license plate detection on the ZedBoard SoC platform,”Advances in Image and Data Processing using VLSI Design, vol. 01, series 2053-2563, IOP Publishing, pp. 15-1 to 15-19, Dec 2021, doi: 10.1088/978-0-7503-3919-3ch15.
  • S. Chhabra and K. Lata, “Key-Based Obfuscation Using Strong Physical Unclonable Function: A Secure Implementation”. In: Abraham, A., Shandilya, S., Garcia-Hernandez, L., Varela, M.(eds) Hybrid Intelligent Systems. HIS 2019. Advances in Intelligent Systems and Computing, vol 1179, Springer, Cham. doi: 10.1007/978-3-030-49336-3_39

  • S. Chhabra and K. Lata, “Key-based Obfuscation using HT-like Trigger Circuit for 128-bit AES Hardware IP Core,” 34th IEEE International System-on-Chip Conference (SOCC), 2021, pp. 164- 169, doi: 10.1109/SOCC52499.2021.9739619.
  • S. Chhabra, V. Dhanwani, V. K. Dhaka and K. Lata, “Design and Analysis of Secure One-way Functions for the Protection of Symmetric Key Cryptosystems,” 24th IEEE International Symposium on VLSI Design and Test (VDAT), 2020, pp. 1-6, doi: 10.1109/VDAT50263.2020.9190432.
  • S. Chhabra and K. Lata, “Hardware Software Co-Simulation of Obfuscated 128-Bit AES Algorithm for Image Processing Applications,” 4th IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2018, pp. 191-194, doi: 10.1109/iSES.2018.00049.
  • S. Chhabra and K. Lata, “Design and Analysis of Logic Encryption Based 128-Bit AES Algorithm: A Case Study,” 15th IEEE India Council International Conference (INDICON), 2018, pp. 1-6, doi: 10.1109/INDICON45594.2018.8987098.
  • S. Chhabra and K. Lata, “Enhancing Data Security using Obfuscated 128-bit AES Algorithm -An Active Hardware Obfuscation Approach at RTL Level,” 7th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2018, pp. 401-406, doi: 10.1109/ICACCI.2018.8554562.
  • A. Bhardwaj, S. Chhabra and K. Lata, “FPGA Implementation of Traffic Light Controller and its Analysis in the Presence of Hardware Trojan,” 7th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2018, pp. 375-380, doi: 10.1109/ICACCI.2018.8554439.
  • S. Chhabra and K. Lata, “Analysis of aes cryptosystem in the existence of hardware trojan,” 6th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2017, pp. 2335-2341, doi: 10.1109/ICACCI.2017.8126195.
  • S. Chhabra and K. Lata, “Obfuscation based Secure 128-bit AES Algorithm Design at the RTL Level,” 5th Global Conference on Cyber Space (GCCS), 2017 Organized by Ministry of Electronics and Information Technology (MEITY), Government of India.
  • S. Chhabra, H. Jain, and S. Saini, “FPGA based hardware implementation of automatic vehicle license plate detection system,” 5th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2016, pp. 1181-1187, doi: 10.1109/ICACCI.2016.7732205.

  • Computer Programming
  • Introduction to Cryptography
  • Digital Circuits and System

  • Computer Programming
  • Introduction to Cryptography
  • Digital Circuits and Systems
  • Digital System Design using FPGAs
  • Hardware Security

  • Assistant Professor: JK Lakshmipat University, Jaipur (Aug 2023-Current)
  • Hardware Security Consultant, under Centre for Hardware Security Entrepreneurship Research & Development (C-HERD): Data Security Council of India, Noida, Uttarpradesh (Nov 2022 - July 2023)
  • Teaching and Research Assistant: The LNM Institute of Information Technology, Jaipur (Aug 2014- July 2022) ).

  • Member, ACM
  • Member, IEEE 96.

  • Recipient of IEEE VLSID (2022-23) Fellowship.
  • Served as a Reviewer for peer-reviewed journals vi. IEEE Consumer Electronics Magazine, IET Information Security, IEEE Access, Springer IJIS, JoCCASA, Springer JoCE, JoSC, JoCC, Scientific Reports and conferences like IEEE ISCAS, IEEE NCC, etc.
  • Served as a Session Chair at the IEEE ICACCI Conference 2017.
  • Received B.Tech. Honours in ECE & won the Best Student Award.
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  • Bachelor of Technology B.Tech

  • Bachelor of Design B.Des

  • Bachelor of Business Administration BBA

  • Bachelor of Business Administration BBA (Fintech)

  • Bachelor of Business Administration BBA (Honours)

  • Master of Design M.Des

  • Master of Technology M.Tech

  • Master of Business Administration MBA

  • Doctor of Philosophy PhD

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