JK Lakshmipat University

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Dr. Gaurav Mani Khanal
Institute of Engineering and Technology


Dr. Gaurav Mani Khanal

Assistant Professor
Institute of Engineering and Technology

Area/ Specialisation

 VLSI, Nanoelectronics, Neuromorphic computing



Member of JKLU faculty since

9th June 2023

Profile Links


  • PhD (Electronics Engineering) from University of Tor Vergata, Rome, Italy (2017).
  • Advance Master Wireless Systems and Related Technology from Polytechnic University of Turin, Italy (2013).
  • M.S. (Microelectronics and System Design) from Liverpool John Moores University, UK. (2010)
  • B.Tech (ECE) from Bundelkhand University, Jhansi (2006).


Dr. Gaurav Mani Khanal is Assistant Professor in the Department of Electronics Engineering at the Institute of Engineering and Technology, JKLU. He has more than 5 years of teaching and research experience in India and Abroad. He completed PhD in Electronics Engineering with focus on Modelling, Fabrication and Application (system development) of novel nanoelectronics device (Memristor) for low power brain inspired electronics system design, from the University of Rome Tor Vergata, Rome, Italy. Dr. Gaurav have hands- on experience on electronics device modeling and circuit design using SPICE and digital system design and synthesis using VERILOG HDL.

Prior to joining the JKLU, he worked as Assistant Professor and Co-coradinator semiconductor research centre at Punjab Engineering College (Deemed to be University), Chandigarh, and also worked as post doctoral research fellow with Professor Gian Carlo Caradrillli’s The Hardware Architecture for Digital Signal Processing Lab located in the Department of Electronic Engineering of University of Rome Tor Vergata.


Dr. Gaurav has expertise in Memristor/Resistive switching device design, modeling, fabrication and characterization. He is an expert user of Spice tools for modeling of CMOS as well as beyond CMOS devices and circuits. He has published two books on VLSI design and has more than more than 12 research articles in the area of Memristor, VLSI design and novel nano-electronics and MEMS devices. He along with Semiconductor research centre team headed by Prof Arun Kumar Singh had organized two  7 days hands on workshops fully sponsored by SERB and DST GOI on Semiconductor devices design modeling, fabrication and characterization.


Recently his Project as (CO-PI) Titled “Memristor- FPGA hybrid hardware system for brain inspired analog computing” has received Funding from Ministry of Electronics & Information Technology (MeitY) under Chips to Start-up (C2S) programme. The project is in collaboration with Dr Arun Kumar Singh (PI) Professor and Co-coordinator of Semiconductor Research Centre, Department of ECE, Punjab Engineering College, Chandigarh and Dr Sanjeev Kumar(CO-PI) Professor & Head (Physics Department), Punjab Engineering College, Chandigarh. Technical collaborators for the projects are Sankalp Semiconductor an HCL Tech Company and Professor Gian Carlo Caradrilli’s Hardware Architectures for Digital Signal Processing Lab, Department of Electronics Engineering, University of Rome “Tor Vergata”, Rome, IT.
Duration: 5 years (Starting 2023) Total Amount: 81 Lakh INR

Teaching Interests
  • CMOS VLSI Design
  • Digital System Design
  • Novel Nanoelectronics devices and Circuits
  • Low Power Electronics system design
Research Interests
  • Brain Inspired Electronics System Design
  • Neuromorphic Engineering
  • Flexible and sustainable Electronics devices and systems
Honours, Awards, and Affiliations



S.No. Name of the Award Awarding Agency Year
1 Best Paper Presenter Award IEEE International Conference on Semiconductor Electronics (ICSE2016), Kuala Lumpur, Malaysia 2016
2 Graduate Research Fellowship University of Rome Tor Vergata, Rome , Italy 2013
3 The Compagnia di San Paolo Fellowship Politecnico di Torino, Turin, Italy 2012


Selected Publications




Authors Title Name of the Journal Vol. Page Year
1 S. Bansal,

A. Das, K.

Prakash, K. Sharma, G.

M. Khanal, N. Sardana,

S. Kumar,

N. Gupta, and A. K. Singh,

Bilayer Graphene/HgCdTe Heterojunction Based Novel GBn Infrared Detectors, Micro and Nanostructure Micro and Nanostructures 169 207345 2022
2 P. Jain, K. Prakash, G.

M. Khanal,

N. Sardana,

S. Kumar,

N. Gupta, and A. K. Singh

Quad-band Polarization Sensitive Terahertz Metamaterial Absorber Using Gemini-Shaped Structure Results in Optics 8 100254 2022
3 K. Prakash,

S. Bansal, P. Jain, S. Garg, G. M. Khanal, S. Kumar, N. Gupta, S. R Kasjoo, A.

K. Singh

Thermoelectric rectification in graphene based Y-junction Micro and Nanostructures 167 207242 2022
4 Gian Carlo Cardarilli, Gaurav Mani Khanal*, Luca Di Nunzio, Marco Re, Rocco Fazzolari, Raj Kumar Memristive and memory impedance behavior in a photo-annealed

ZnO–rGO thin-film device

Electronics 9 (2) 287 2020
5 Silvestri, F., Acciarito, S., &

Khanal, G. M.

Relationship between

mathematical parameters of modified Van der Pol oscillator model and ECG morphological features


Int. J. Adv. Sci. Eng. Inf. Techno (Scopus)

9 601-608 2019
6 Khanal, G.M.;

Acciarito, S.; Cardarilli, G.C.; Chakraborty, A.; Nunzio, L.D.; Fazzolari, R.;Cristini, A.; Re, M.; Susi,G

Synaptic behaviour in ZnO–rGO composite thin film memristor Electronics Letters 53(2) 296-298 2017
7 Simone Acciarito, Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Rocco Fazzolari, Gaurav Mani Khanal, Marco Re, Gianluca Susi Hardware design of LIF with latency neuron model with memristive STDP synapses Integration the VLSI Journal 59 81-89 2017
8 Silvestri, F., Acciarito, S., Cardarilli, G. C., Khanal,

G. M.,

Nunzio, L. D., Fazzolari, R., & Re, M.

FPGA Implementation of a Low-power QRS extractor LNEE series, Springer, Cham (Scopus)

an Society

512 9-15 2017
9 Acciarito, S., Cardarilli, G. C., Khanal,

G. M.,

Matta, M.,

Re, M.,

Silvestri, F., & Simone, L.

Digital Architecture of Next Generation Spacecraft Tracker Based on Wideband DOR LNEE series, Springer, Cham (Scopus)


512 17-24 2017
10 Acciarito, S., Giardino, D., Khanal, G. M., Re, M.,

Silvestri, F., & Sergio, S.

FPGA Implementation of a Channelizer with 2048 Channels utilizing USRP-SDR platform for satellite communications LNEE series, Springer, Cham (Scopus) 512 25-31 2017
11 Khanal, G. M, Acciarito, S., Cardarilli, G.C ZnO-rGO composite thin film resistive switching device: LNEE series, Springer, 429 117-123 2016
12 Acciarito, S., Cardarilli, G.C., Di Nunzio, L., Fazzolari, R., Khanal, G.M., Re, M. Compressive Sensing Reconstruction for Complex System: A Hardware/Software Approach LNEE series, Springer, Cham (Scopus) Environment

and Society

429 192-200 2016








  1. Publications (Conference)


1 S. Garg, B. Sharma, G. M. Khanal, N. Gupta, R. Syal, S. Kumar, S. R.

Kasjoo, and A. K. Singh

Simulation of MoS2 based Asymmetric Nanochannel rectifier IEEE NANO (Accepted Manuscript) 2022
2 Acciarito, S., Cristini, A., Di Nunzio, L., Khanal, G. M., & Susi, G. An a VLSI driving circuit for memristor-based STDP IEEE Conference on Ph.

D. Research in Microelectronics and Electronics (PRIME)

1-4 2016
3 Khanal, Gaurav Mani and Cardarilli, GianCarlo and Chakraborty, Abhishek and Acciarito, Simone and Mulla, Mohammad Yusuf and Di Nunzio, Luca and Fazzolari,

Rocco and Re, Marco


composite thin film discrete memristor

IEEE International Conference on Semiconductor Electronics (ICSE)  




  1. Books/Reports/Chapters/General articles




Title with page Nos. and date of publication Type of Book & Authorship Publisher & ISSN/ISBN No.
1 Advanced VLSI Technology: Technical For competitive ISBN-10:
Questions with Solutions River Publishers exam and 877022174X,
Series in Circuits and Systems, Denmark May 2020 interview ISBN-13: 9788770221740
2 Basic VLSI Design Technology: Technical For competitive ISBN-10:
Questions and Solutions River Publishers exam and 8770221588,
Series in Circuits and Systems, Denmark May 2020 interview ISBN-13:


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